There is a semiconductor device in which an element isolation structure in which an insulating film is formed in a high aspect ratio trench whose aspect ratio corresponding to a ratio of a depth of the trench to a width of the trench is higher than 1 (deep trench isolation (DTI) structure) is provided in a main surface of a semiconductor substrate. In addition, there is known a substrate contact plug which is formed in the deep trench like this formed in the main surface of the semiconductor substrate and is connected to the semiconductor substrate at the bottom surface of the trench.
Further, a seal ring made of a metal member formed in an outer periphery of a semiconductor chip is known as a structure to prevent moisture from entering a circuit region of the semiconductor chip due to a dicing process performed to obtain a plurality of semiconductor chips by cutting a semiconductor wafer, and to prevent metallic contamination of the circuit region due to the dicing process.
Patent Document 1 (Japanese Patent Application Laid-Open Publication No. 2011-66067) and Patent Document 2 (Japanese Patent Application Laid-Open Publication No. 2011-151121) disclose an element isolation using a deep trench.
Patent Document 3 (Japanese Patent Application Laid-Open Publication No. 2015-37099) discloses a structure in which a plug is formed in a deep trench and the plug is connected to a semiconductor substrate.
Patent Document 4 (Japanese Patent Application Laid-Open Publication No. H8-37289) discloses a structure of a seal ring.